Technical Field
The present invention relates to a comparison circuit that compares the magnitudes of voltages, and particularly to a circuit that suppresses an influence due to a leak current or noise of a circuit element at a high temperature and performs a highly accurate voltage comparison.
Background Art
In electronic circuits in general, a comparison circuit has been used as a circuit that compares a plurality of voltages and determines the magnitudes thereof (refer to, for example, a Patent Document 1).
A circuit diagram of one example of a conventional comparison circuit is shown in FIG. 9. The conventional comparison circuit uses a comparator (comparator) and determines whether a voltage of a difference between two input voltages is larger or smaller than a predetermined voltage. In this comparison, a problem arises in that an offset voltage (input offset voltage) or noise included in the comparator becomes a factor of an error and the accuracy is degraded. The above input offset voltage is generated due to variations in the characteristics of each element that configures an input circuit of the comparator by way of example. Further, the above noise is generated due to flicker noise of a single transistor that configures a circuit, or thermal noise of a single transistor or a resistance element.
In order to reduce the influence of the offset voltage of the above-described comparator, the comparison circuit shown in FIG. 9 takes the following configuration. The comparison circuit has a comparator 5, a switch S3 connected between an inversion input terminal N3 of the comparator 5 and an output terminal, a capacitor 3 connected between the inversion input terminal N3 of the comparator 5 and an input terminal N1, a switch S4 connected between a non-inversion input terminal N4 of the comparator 5 and a comparison voltage input terminal Nref, a switch S1 connected between the non-inversion input terminal N4 of the comparator 5 and a connection point N41, a capacitor 4 connected between an input terminal N2 and the connection point N41, and a switch S2 connected between the connection point N41 and a comparison voltage input terminal N0. Here, a voltage of the comparison voltage input terminal N0 is taken to be V0, a voltage of the comparison voltage input terminal Nref is taken to be Vref, a voltage of the input terminal N1 is taken to be V1, a voltage of the input terminal N2 is taken to be V2, a voltage of the inversion input terminal N3 of the comparator 5 is taken to be V3, a voltage of the non-inversion input terminal N4 of the comparator 5 is taken to be V4, and a voltage of the output terminal of the comparator 5 is taken to be Vo. Further, the input offset voltage of the comparator 5 is taken to be Voa.
The comparison circuit of FIG. 9 is operated with the switches S1 to S4 being controlled as shown in FIG. 10. One cycle for the operation consists of a sample phase φ1 and a comparison phase φ2. In the sample phase φ1, the switch S1 is turned off and the switches S2 to S4 are turned on. In the comparison phase φ2, the switch S1 is turned on and the switches S2 to S4 are turned off. Further, φ1 or φ2 attached to the ends of the voltages of each connection point and each terminal is taken to indicate the voltages in the sample phase φ1 or the comparison phase φ2 respectively.
In the sample phase φ1, the switch S1 is turned off and the switch S2 is turned on so that ΔVC4φ1=V0−V2φ1 is charged in the capacitor 4. V4φ1=Vref since the switch S4 is on. Since the comparator 5 operates as a voltage follower circuit since the switch S3 is on, and has the input offset voltage Voa, Voφ1=V4φ1+Voa. Further, since the switch S3 is on, V3φ1=Voφ1, i.e., V3φ1=Vref+Voa. ΔVC3φ1=V3φ1−V1φ1=Vref+Voa−V1φ1 is charged in the capacitor 3. The electrical charges accumulated in the capacitor 3 and the capacitor 4 in the sample phase φ1 are summarized as follows:ΔVC3φ1=Vref+Voa−V1φ1  (43)ΔVC4φ1=V0−V2φ1  (44)
In the comparison phase φ2, the switches S2 to S4 are turned off and the switch S1 is turned on. Since ΔVC3φ1 expressed in the equation (43) is held in the capacitor 3, the voltage V3 is as follows:V3φ2=V1φ2+ΔVC3φ1  (45)On the other hand, since ΔVC4φ1 expressed in the equation (44) is held in the capacitor 4, the voltage V4 is as follows:V4φ2=V2φ2+ΔVC4φ1  46)
At last, the voltage V3 expressed in the equation (45) and the voltage V4 expressed in the equation (46) are compared by the comparator 5, and a high level or a low level is output from the output terminal. Considering the input offset voltage Voa of the comparator 5, the voltages compared by the comparator 5 are as follows:(V4φ2+Voa)−V3φ2={(V2φ2−V1φ2)−(V2φ1−V1φ1)}−(Vref−V0)  (47)It has been shown that the input offset voltage Voa of the comparator 5 is not included in the equation (47) and the offset voltage is canceled. Accordingly, in the comparison phase φ2, the comparator 5 compares the input voltage component {(V2φ2−V1φ2)−(V2φ1−V1φ1)} and the reference voltage component (Vref−V0). Thus, it is possible to realize a comparison circuit from which the influence of an offset voltage component of the comparator, which becomes an error factor, is removed and which provides a high accuracy output with small error.